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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:59:52 12/04/2014 
-- Design Name: 
-- Module Name:    MEM_WB - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MEM_WB is
    Port ( wb_in : in  STD_LOGIC;
           rd_in : in  STD_LOGIC_VECTOR(3 downto 0);
           data_in : in  STD_LOGIC_VECTOR (15 downto 0);
           clk : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR (15 downto 0);
           wb_out : out  STD_LOGIC;
           rd_out : out  STD_LOGIC_VECTOR(3 downto 0));
end MEM_WB;

architecture Behavioral of MEM_WB is

begin
	process(clk)
	begin
		if clk'event and clk='1' then
			data_out<=data_in;
			wb_out<=wb_in;
			rd_out<=rd_in;
		end if;
	end process;
end Behavioral;

